FFE control and readback now working. Output enable is now the only thing left to have full support for a TX-only BERT (aka a serial pattern generator).
Error insertion will come later but I don't have support for that in the API yet (the MultiLane BERT has support in the SDK but I don't think I ever added it in the scopehal driver).
I'll probably do some minimal timebase controls (just 1/2, 1/4, 1/8, 1/16 sub-rate modes without any PLL reconfiguration) next, and probably custom pattern support, before moving on to building the receiver.
Also need to add APIs to scopehal to say "don't show refclk controls because this BERT doesn't have ext ref in/out ports".
The "real" UltraScale+ based dedicated BERT I'm building later on will of course have this and more. The crossbar BERT is more of a minimalistic "as long as I have SERDES on the FPGA let me pin them out" deal.