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I have released Sentinel v0.1.0-beta.2.

Sentinel is my microcoded RISC-V CPU core written in Amaranth. It fits in ~1000 LUTs and ~400 FFs on an ice40 FPGA, and implements RV32I_Zicsr and the Machine Mode privileged spec, and passes the RISCOF and RISC-V Formal test suites.

Ready-to-use Verilog is available here: https://codeberg.org/cr1901/sentinel/releases/tag/v0.1.0-beta.2

Sentinel is also available on PyPI now: https://pypi.org/project/sentinel-cpu/

If you wish to play with the source, follow the Quick Quick Start:

https://codeberg.org/cr1901/sentinel