@kbm0 @gsuberland and or1k iirc
Conversation
Notices
-
Embed this notice
✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Saturday, 22-Nov-2025 16:05:37 JST
✧✦Catherine✦✧
-
Embed this notice
Ken Milmore (kbm0@mastodon.social)'s status on Saturday, 22-Nov-2025 16:05:38 JST
Ken Milmore
@gsuberland Isn't ARM assembly the same? ldr and str take the register first, address second, regardless of direction.
-
Embed this notice
Graham Sutherland / Polynomial (gsuberland@chaos.social)'s status on Saturday, 22-Nov-2025 16:05:40 JST
Graham Sutherland / Polynomial
you know what the most cursed thing is about riscv? the assembly format lacks semantic consistency.
this is how they write the load and store instructions:
lw a0, 4(sp)
sw a0, 4(sp)the first one loads a word from the memory address sp+4 into register a0. the second one stores the word from register a0 into the memory address sp+4. so the first one assigns right to left, and the second assigns left to right.
cursed.
-
Embed this notice