Conversation

Notices

1. Embed this notice
   ✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Thursday, 13-Nov-2025 17:36:38 JST ✧✦Catherine✦✧

   in reply to

   • TheZoq2
   • Lukas

   @thezoq2 @karotte it does have a mandatory 50ns glitch filter...

   • Embed this notice
     TheZoq2 (thezoq2@mastodon.social)'s status on Thursday, 13-Nov-2025 17:36:39 JST TheZoq2

     in reply to

     • Lukas

     @karotte I'd be curious how many i2c targets actually ignore clocks that are too fast

   • Embed this notice
     Lukas (karotte@chaos.social)'s status on Thursday, 13-Nov-2025 17:36:41 JST Lukas

     in reply to

     It's vaguely inspired by I²C and claims to be backwards-compatible with it by clock pulses being shorter than what the I²C spec permits, so I²C targets should ignore I3C traffic.

     Addressing still happens in open-collector mode, but actual data transfer is done in push/pull mode at much higher speed. So no more clock streching, yay!

     In-band interrupts are supported as well as canonical way to reset targets.

     🧵 2/2

   • Embed this notice
     Lukas (karotte@chaos.social)'s status on Thursday, 13-Nov-2025 17:36:42 JST Lukas

     If I²C was so good, why didn't they make I3C… oh wait they did!

     First heard about it ~10 years ago and didn't think much of it as there wasn't any public documentation by the MIPI alliance.

     Over the past few months however I noticed it popping up in SoC and sensors, so I had a closer look at what it is all about: 🧵 1/2