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  1. Embed this notice
    Alex Russell (slightlyoff@toot.cafe)'s status on Friday, 10-Jan-2025 17:31:48 JST Alex Russell Alex Russell

    For the Performance Inequality Gap series, I'm gathering new data points in charts that I'd only talked to in prose in previous years. One of those is the difference between the various market segements looks at by price, with the Flagships clocking the new, unlocked cost of the fastest chip in each line, while the lower-end lines capture the mid-tier and low-end segments from various manufacturers.

    The blue line that has never bumped above $375? That's worldwide average selling price.

    In conversation about 5 months ago from toot.cafe permalink

    Attachments


    1. https://assets.toot.cafe/media_attachments/files/113/802/901/200/450/709/original/8dd124804ecc237f.png
    • Embed this notice
      Alex Russell (slightlyoff@toot.cafe)'s status on Friday, 10-Jan-2025 17:31:46 JST Alex Russell Alex Russell
      in reply to
      • Josh Simmons

      @dotstdy The important thing that web developers need to understand is that expensive phones are rare, and cheap phones are everywhere. And that cheap phones are *much* slower than anything they've used in a long time.

      Discussions of relative L1D and L1P sizings per core across different manufacturers (e.g.) isn't useful detail, so I omit it.

      In conversation about 5 months ago permalink
      MortSinyx likes this.
    • Embed this notice
      Josh Simmons (dotstdy@mastodon.social)'s status on Friday, 10-Jan-2025 17:31:47 JST Josh Simmons Josh Simmons
      in reply to

      @slightlyoff process also impacts the caches, not just frequency directly. caches are large and power hungry. (cost probably still bigger issue, but yeah, and well, process is also just a cost. one does not simply steal tsmc allocation from apple)

      In conversation about 5 months ago permalink
    • Embed this notice
      Alex Russell (slightlyoff@toot.cafe)'s status on Friday, 10-Jan-2025 17:31:47 JST Alex Russell Alex Russell
      in reply to
      • Josh Simmons

      @dotstdy Yes? Obviously? Caches and associated ARBs aren't free, and in the die shots I've worked through for various generations of Android and iOS SoCs, you can see almost as much ARB space on A-series parts as actual cache circuitry. Shrinks help them too.

      These are choices about how often you're going to stall for an eternity, and what else you're going to boot of the die (in Apple's case, the radio that Qualcomm wants to sell).

      But that's not relevant to webdevs.

      In conversation about 5 months ago permalink
    • Embed this notice
      Alex Russell (slightlyoff@toot.cafe)'s status on Friday, 10-Jan-2025 17:31:48 JST Alex Russell Alex Russell
      in reply to

      The thing folks at the low-end are mostly missing out on is performance, which is dominated by combined L1 + L2 + L3 + SLC on-package caches, with process-shrink-driven frequency scaling not far behind:

      In conversation about 5 months ago permalink

      Attachments


      1. https://assets.toot.cafe/media_attachments/files/113/802/929/386/393/496/original/948b0b07d480f28a.png

      2. https://assets.toot.cafe/media_attachments/files/113/802/935/932/187/824/original/350a4c3d8a9d7d1e.png

      3. https://assets.toot.cafe/media_attachments/files/113/802/944/105/549/421/original/e7d2ea961a93c8ec.png

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