Finally the last 1.8V power domain: GTX_1V8. This is the VCCAUX supply for the SERDES quad on the FPGA.
Average is right where I want, 1.796V.
Using a MYMGK for this with 4A rated output was probably overkill and the very light load is probably the reason the ripple is slightly out of spec (14.81 mV p-p / 1.63 mV RMS, datasheet wants no more than 10 mV p-p).
That said, I might still be OK since this is the ripple measured on the plane close to the DC-DC and I actually have a 4.7 uF cap across the via going to the FPGA ball that will attenuate some of the sharper spikes.
At some point I might try to take a differential measurement across that cap but for now I think I'll call this "not great, but probably tolerable". The main impact of a bit more ripple here would be degraded jitter performance on the GTX (since this is the PLL supply) and I'm seeing eyes that look perfectly fine.