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   Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Monday, 19-May-2025 11:53:42 JST Andrew Zonenberg

   in reply to

   @whitequark As of now I have a native sram interface to the memory (xilinx UltraRAM) but the latency is variable due to both the potential for me to add arbitration in front of it, and because I will likely be adding and removing pipeline stages for timing closure as the design evolves.

   So i don't want my read-side logic to make any assumptions about latency