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   Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Monday, 05-May-2025 18:21:22 JST Andrew Zonenberg

   in reply to

   @abrasive @whitequark I loaded USER1 into IR (this was a Spartan-6 FPGA) and then entered SHIFT-DR state.

   And free-ran TCK.

   The debug bridge would constantly shift in idle words if you had no data to send, and check the response data from the DUT for a preamble. As soon as it saw a 55 55 55 D5 it knew the DUT was sending traffic and would parse it appropriately.

   So you effectively had two independent unidirectional streams of 32-bit words sent bit serial, each synchronous to TCK but with no tight coupling to each other. This let me use large bulk transfers over the MPSSE and completely eliminated polling, which was far more efficient.