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3d render of a SOIC chip next to a board edge with castellated pads spaced for its pins, as if you're supposed to solder the chip to the edge of the board

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https://sparkly.uni.horse/system/media_attachments/files/114/061/456/026/119/986/original/d1eb6d3305d4ce29.png

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  1. Embed this notice
    emily, blinkenlight witch (emily@sparkly.uni.horse)'s status on Tuesday, 25-Feb-2025 09:51:24 JST emily, blinkenlight witch emily, blinkenlight witch
    in reply to

    @nekoewen try my new thing

    In conversation 2 months ago from sparkly.uni.horse permalink
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GNU social JP is a social network, courtesy of GNU social JP管理人. It runs on GNU social, version 2.0.2-dev, available under the GNU Affero General Public License.

Creative Commons Attribution 3.0 All GNU social JP content and data are available under the Creative Commons Attribution 3.0 license.

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