Schematic showing LMR70503 paired with 2x 10 uF MLCC at input, CTS520,L3F diode, MLZ2012N4R7LTD25 inductor, and 2x 22 uF MLCC output caps.
https://files.ioc.exchange/media_attachments/files/112/030/389/107/592/700/original/65fed99a775c5a35.png
Also, I now have 2.2 GB of waveform data saved (almost, but not exclusively, from the rail validation work). Will be useful to be able to go back and look at saved waveforms and do A/B testing showing the impact of rework.
So now the question is, where do I go from here?
The SMPS is fairly straightforward, basically reference schematic for the LMR70503.
Layout wise, I see one potential issue: while the bulk caps (at least the nearest one) are connected to the chip on the top layer on the 3V3 side, the ground is not (only by vias to layer 2). So that adds a bit of loop inductance.
Not much, but some.
For initial rework, I'm thinking of shoving an 0.47 uF 0402 X7R across the C2/C3 GND/3V3 vias. Unless anybody else has better ideas?
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