Closeup of the PCB showing cables attached to connectors and test points

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   Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:36:16 JST Andrew Zonenberg

   in reply to

   GTX bringup isn't happening before bed. I always forget how many clocks and general infrastructure is needed even to get a PRBS out.

   But I have everything cabled up for tomorrow and got a small amount (not nearly enough) of much needed bench tidying done.

   3V0_N still isn't coming up, I'll figure that out later on. It's not needed for anything but the single ended front panel CDR trigger input. Losing that (when I already have two differential front panel SERDES inputs) isn't a huge deal even if I never get it working.

   For now, 99% of the board functionality seems to be ready to go so I can start writing firmware and gateware tomorrow.

   At some point I'll probably do some more extensive defluxing of the reworked areas but it doesn't have to be in the next day or two. Saving the heatsink for later just in case I find more stuff that needs bodging near the FPGA.