Notices by Tube❄️Time (tubetime@mastodon.social)

new project drop: this is the design for my IBM Micro Channel DBA-ESDI drive emulator. super early alpha version!

https://github.com/schlae/difnif

found someone on the eevblog forums who said they reverse engineered a schematic. naturally, they never posted it and then fell off the face of the earth

doing a little digging with a sharp knife. you can see the anti-pad openings in the copper pour on the layer directly underneath. but there's no copper in the via barrel for me to solder to. it's all dissolved away.

drilled down until I found copper in the via barrel. I wonder if this will work.

this is why. there's one via that's broken. just one. that's the only thing standing in between me and a working card. I'll have to excavate to try and find some copper I can solder to.

the trace leading to it is cut so I can check for the ESD diode in the FPGA on the other side of the via to confirm when it's been reconnected.

so it passes all the tests except for the VRAM serial readout tests for one bank (bank 1, choices are bank 0-9). think I know why

(screenshot is from the self test for a different card but you get the idea)

still working on this. I've fixed a bunch of traces, let's see if it passes the self test

my hunch that i need the cables plugged in to pass the test might be right. looks like this card works now!!!

well, there's good news and bad news. my via fix actually worked! but now there's a problem with the comparators. :(

here's what i'm trying to do. the top image is a normal via. you can see this is an 8 layer board, and the via has no connections to inner layers. it just goes straight through. then in the middle image, the gunk has etched out the copper in the top part of the via. in the bottom image, i've drilled out the material to expose fresh copper, then jammed a wire in there. there's a little solder which (hopefully) wetted to the via barrel.

it was easier to just remove the resistor array completely so i could clean up the pads and the resistor leads.

yeah there are corroded solder joints on that resistor array. at least 1 high resistance connection.

pod1 and pod2 are on the connector nearest the edge of the board (middle connector is for 3 and 4). pod1 chips are on the bottom of the board, pod2 chips on the top. and bit 2 is on this wire coming off the connector. but i suspect a problem with the resistor array tied to the outputs of the comparator chip.

whoops, spoke to soon. it fails 1 of the comparator tests. now i just have to figure out which one it is physically on the board...

pulled the chip off the other card. uh that entire via was corroded away, even part of the trace on the other side. no wonder I couldn't find any copper.

that worked! the card passes all the self tests now.

quick diagram of the resistor array, a 4816P-B07-000. the comparator output goes to pins 1, 3, 5, and 7. pins 2, 4, 6, and 8 are grounded (so the 670 ohm resistors go to ground). the outputs to the FPGA seem to be on pins 10, 12, 14, and 16. the remaining pins go...elsewhere. i suspect it's some sort of termination network that might do some level shifting. perhaps the comparators have ECL outputs or something.

the acquisition ASICs are not 100% figured out yet.

good progress the last few days. i've mostly figured out the pinouts of the HP custom comparator chips and timing zoom chips.

figuring out the mapping between the comparator inputs and outputs. these chips are not off the shelf!